ILD

ethernet phy
作者:Yuan Jianpeng 邮箱:yuanjianpeng@xiaomi.com
发布时间:2022-1-26 站点:Inside Linux Development

Ethernet MAC Block Diagram

Network Models

MAC Controller aka Ethernet Controller

An Ethernet controller or Ethernet Media Access Controller is hardware responsible for interaction with the wired, optical or wireless transmission medium. Transmission medium is implemented by the PHY Device.

MAC controller is majorly implemented in Hardware.

In Software The MAC sublayer and the logical link control (LLC) sublayer together make up the data link layer.

Functions of Ethernet MAC

Ethernet PHY

ethernet-phy

Major Functions of PHY Layer

Ethernet physical layer Include

Ethernet Driver

Ethernet drivers is a software programs that provide hardware-software interaction between the operating system and its local area network (LAN) port

Ethernet Driver Functions

Interfaces between a MAC and a PHY

MII (Media Independent Interface)

Media independent: Different media (twisted pair, fiber optic etc) can be used without redesigning or replacing the MAC hardware

Management Data Input/Output (MDIO)

MII set of registers

RegisterDescription
Basic Mode Configuration (#0)Mode?
Status Word (#1)PHY Status
PHY Identification (#2, #3)Unique ID assigned to a PHY
Ability Advertisement (#4)Ability to be advertised during negotiation
Link Partner Ability (#5)Peer Ability after negotiation
Auto Negotiation Expansion (#6)Peer Ability after negotiation

MII Status Word and Descrition

Status Bit valueDescrition
0x7800Capable of 10/100 HD/FD (most common)
0x0020Autonegotiation complete
0x0010Remote fault
0x0004Link established

MII Transmitter signals (7 Signals)

Signal nameDescritionDirection
TX_CLK25 MHz: 100 Mbit/s, 2.5 MHz: 10 Mbit/sPHY to MAC
TXD0 ... TXD3Transmit data bitsMAC to PHY
TX_EN1: transmission, 0: idleMAC to PHY
TX_ERTransmit errorMAC to PHY

MII Transmitter signals (9 Signals)

Signal nameDescritionDirection
RX_CLK25 MHz: 100 Mbit/s, 2.5 MHz: 10 Mbit/sPHY to MAC
RXD0 ... RXD3Receive data bitsPHY to MAC
RX_DVReceive Data ValidPHY to MAC
RX_ERReceive errorPHY to MAC
CRSCarrier sensePHY to MAC
COLCollision detectPHY to MAC

MII Limitations (Too Many IO Lines)

RMII (Reduced media-independent interface)

RMII Signals (10 Signals)

Signal nameDescritionDirection
REF_CLKContinuous 50 MHzMAC to PHY or External



TXD0, TXD1Transmit data bitsMAC to PHY
TX_EN1: clock data on TXD0 and TXD1MAC to PHY



RXD0, RXD1Receive data bitsPHY to MAC
CRS_DVMultiplexed on alternate clock cyclesPHY to MAC
RX_ERReceive errorPHY to MAC



MDIOManagement dataBidirectional
MDCManagement ClockMAC to PHY

MDIO/MDC interface

GMII (gigabit media-independent interface)

Transmitter signals

Signal nameDescriptionDirection
GTXCLKClock signal for gigabit TX signals (125 MHz)MAC to PHY
TXCLKClock signal for 10/100 Mbit/s signalsPHY to MAC
TXD[7..0]Data to be transmittedMAC to PHY
TXENTransmitter enableMAC to PHY
TXERTransmitter error (used to corrupt a packet)MAC to PHY

Receiver signals

Signal nameDescriptionDirection
RXCLKReceived clock signal (recovered from incoming received data)PHY to MAC
RXD[7..0]Received dataPHY to MAC
RXDVSignifies data received is validPHY to MAC
RXERSignifies data received has errorsPHY to MAC
COLCollision detect (half-duplex connections only)PHY to MAC
CSCarrier sense (half-duplex connections only)PHY to MAC

Management signals

Signal nameDescriptionDirection
MDIOManagement dataBidirectional
MDCManagement ClockMAC to PHY

RGMII (reduced gigabit media-independent interface)

RGMII signals

Signal nameDescriptionDirection
TXCClock signalMAC to PHY
TXD[3..0]Data to be transmittedMAC to PHY
TX_CTLMultiplexing: Tx enable and Tx errorMAC to PHY
RXCReceived clock signal (recovered from incoming received data)PHY to MAC
RXD[3..0]Received dataPHY to MAC
RX_CTLMultiplexing: Rx Data valid and Rx errorPHY to MAC
MDCManagement interface clockMAC to PHY
MDIOManagement interface I/OBidirectional

SGMII (serial gigabit media-independent interface)

The serial gigabit media-independent interface (SGMII) is a variant of MII, a standard interface used to connect an Ethernet MAC block to a PHY. It is used for Gigabit Ethernet but can also carry 10/100 Mbit/s Ethernet.

HSGMII (high serial gigabit media-independent interface)

QSGMII (quad serial gigabit media-independent interface)

XGMII (10-gigabit media-independent interface)



参考

https://github.com/hoodaajay99/linux-kernel-device-drivers/blob/master/docs/36-Network-Drivers/04-MAC-PHY-and-MII-Interface/MAC-PHY-and-MII-Interface.md


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